HAL v3.3 releases: The Hardware Analyzer
HAL- Hardware Analyzer
Hardware Analyzer (HAL) [/hel/] is a comprehensive reverse engineering and manipulation framework for gate-level netlists focusing on efficiency, extendability, and portability. HAL comes with a fully-fledged plugin system, allowing it to introduce of arbitrary functionalities to the core.
Features
- Natural directed graph representation of netlist elements and their connections
- Support for custom gate libraries
- High-performance thanks to optimized C++ core
- Modularity: write your own C++ Plugins for efficient netlist analysis and manipulation (e.g. via graph algorithms)
- A feature-rich GUI allowing for visual netlist inspection and interactive analysis
- An integrated Python shell to exploratively interact with netlist elements and to interface plugins from the GUI
Changelog v3.3
- WARNING: this release partially breaks the
GateType
API, please make sure to adjust your code accordingly. - added user action system to enable recording and reverting actions within the GUI
- moved most GUI actions to the new user action system, including interactions with the graph view and view management
- user actions can be recorded and exported as a macro file allowing easier debugging and crash reporting
- recording of the user actions is automatically dumped on crash
- users can now revert actions executed within the GUI
- rebuild the settings system from scratch to allow for easier integration of new settings
- theme setting (and many others) can now be changed during the session
- added a warning when attempting to assign a keybinding that is already in use
- added incremental search for settings
- added setting to enable/disable extra window to list all executed instances from UserAction
- added new
Move to module ...
dialog- allows to create new module or select from existing modules
- existing modules can be selected from a table, tree-view, or using a module picker within the graph view
- enables searching for existing modules
- added cursor to indicate that user is in module pick mode
- added successor / predecessor utilities to gate and module context menu
- shortest path between two gates can be highlighted or added to current view
- predecessors or successors can be highlighted or added to the current view up to a user-specified depth
- different grouping colors can be assigned depending on the distance from the origin
- common predecessors or successors can be found and added to view
- improved layouter
- omit repeated layouting during an ongoing activity
- show progress bar during layouting
- allow user to abort layouting
- preserve graph view location of gate when moving it to new module
- fixed routing errors for complex cable swaps
- fixed multiple connections of a single net to the same gate not being shown properly
- fixed incorrect placement of new gates and modules in cone view when navigating starting from a net
- added generic SMT solver interface.
- added translation from
BooleanFunction
to SMT-LIB. - added
BooleanFunction::Node
data structure to extend functionality to generic ASTs. - added support for z3 and boolector SMT solvers.
- added cpp-subprocess library to handle communication with SMT solver.
- added Boost Spirit x3 library to generate grammar-based parser from SMT-LIB models to C++ data structures.
- added translation from
- improved handling of properties for special gate types such as LUTs and FFs.
- properties that only apply to special gate types have been moved out of the
GateType
class and into a designatedGateTypeComponent
- added functions to retrieve a gate type’s components based on some filter condition
- added special components dealing with RAM properties
- properties that only apply to special gate types have been moved out of the
- improved netlist parsers
- split VHDL and Verilog parsers into two independent plugins
- netlist parsers now take the path to the netlist file as input instead of a
std::stringstream
- added support for
Z
andX
assignments to Verilog and VHDL parsers - added
tri
as a synonym forwire
to the Verilog parser - fixed netlist parsers assigning wrong order of inputs for some multi-bit signals
- improved netlist writers
- netlist writers now take the output path as input instead of a
std::stringstream
- removed broken VHDL writer (will not be supported until further notice)
- entirely new Verilog writer that respects module hierarchies
- added GEXF netlist writer, e.g., for netlist analysis within Gephi
- netlist writers now take the output path as input instead of a
- expanded
netlist_utils
- added function
get_common_inputs
to get inputs that are common across multiple gates - added function
replace_gate
to replace a gate with an instance of another gate type - added function
get_gate_chain
andget_complex_gate_chain
to find gates that are arranged in a chain - added function
get_shortest_path
to compute the shortest path between two gates - added function
get_next_gates
to get the predecessors or successors of a gate up to a user-specified depth - added function
get_partial_netlist
to export parts of a netlist as a netlist instance
- added function
dataflow_analysis
plugin- can now take groups of flip-flops as input that should not be touched during analysis
- this is meant to aid the dataflow analysis by passing control registeres identified beforehand, which prevents them from being merged into the datapath
- new internal event system
- binds event handlers to a netlist instance
- facilitates listening to the events of selected netlists only
- improved search
- all searchbars now come with options for “Exact Match” and “Case Sensitive” search, as well as a “Clear” button
- added search icons to the Python editor and the module widget
- disabled the search filter whenever the searchbar is not visible within a widget
- miscellaneous API changes and additions
- added function
is_top_module
to classModule
to determine whether a module is the top module - added function
get_nets
to classModule
to get all nets that are connected to any of the gates or submodules of a module - added functions
is_gnd_net
andis_vcc_net
to classNet
to determine whether a net is connected to GND or VCC - added functions
operator==
andoperator!=
to classesNetlist
,Gate
,Net
,Module
, andEndpoint
- added Python bindings for
netlist_serializer
- added function
- miscellaneous GUI changes and additions
- added
Save As...
option to save.hal
files under a different name - added
Export ...
menu to export the netlist using any of the registered netlist writers - added
Remove from view
action to context menu for gates and modules - added context menu options to close multiple view tabs at once
- added an indicator showing whether views have been modified
- added HAL version number to the info shown in
About
- added
Fold parent module
option to module context menu - when trying to create a view for a module that is already associated with an (unchanged) view, the existing view is activated instead of creating a new view
- added
- bugfixes
- fixed selection details not being updated immediately when renaming or changing a type
- fixed navigation bug where ports and nets did not match for modules
- fixed list of navigation targets containing duplicates and/or loops
- fixed drag’n’drop bug related to negative coordinates
- fixed liberty parser aborting on unknown
pg_type
- fixed stylesheets
- fixed improper handling of GND and VCC nets within the
solve_fsm
plugin - fixed module port names not being freed when reassigned a new name
- fixed segfault when no VCC or GND gate is present within a netlist
Install && Tutorial
Copyright (c) 2019 Ruhr-Universität Bochum, Lehrstuhl für Eingebettete Sicherheit. All Rights Reserved.
Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann (“ORIGINAL AUTHORS”). All rights reserved.