HAL v4.1 releases: The Hardware Analyzer
HAL- Hardware Analyzer
Hardware Analyzer (HAL) [/hel/] is a comprehensive reverse engineering and manipulation framework for gate-level netlists focusing on efficiency, extendability, and portability. HAL comes with a fully-fledged plugin system, allowing it to introduce of arbitrary functionalities to the core.
Features
- Natural directed graph representation of netlist elements and their connections
- Support for custom gate libraries
- High-performance thanks to optimized C++ core
- Modularity: write your own C++ Plugins for efficient netlist analysis and manipulation (e.g. via graph algorithms)
- A feature-rich GUI allowing for visual netlist inspection and interactive analysis
- An integrated Python shell to exploratively interact with netlist elements and to interface plugins from the GUI
Changelog v4.1
- selection details
- module icons reflect module color
- gate icons shape according to gate type
- user setting to adjust size of or omit icon in upper right corner
- project import/export
- added export feature: generate zipped project including external gate libraries and python source files
- added import feature by extracting zipped project
- added quazip library sources (deps) since recent distributions no longer link binary packages against qt5
- netlist parsers
- added (limited) support for ‘defparam’ statements to Verilog parser
- added support for pin assignments by order instead of name to Verilog and VHDL parser
- GUI comments
- user can add comments to gates and modules to take notes on the reverse engineering progress
- comments are shown in the graph view (as little notes on the gate/module boxes) and in the selection details widget
- plugin
netlist_preprocessing
- collection of utility functions preparing a raw netlist for further analysis
- remove LUT fan-in endpoints that do not show up in the LUT’s boolean function via
remove_unused_lut_inputs
- remove buffer gates via
remove_buffers
, also dynamically by analyzing Boolean function and connected inputs - remove redundant gates via
remove_redundant_logic
, i.e., gates of equal type with identical inputs - remove unconnected gates/nets via
remove_unconnected_gates
andremove_unconnected_nets
- simplify LUT configuration strings based on constant inputs via
simplify_lut_inits
- plugin
bitorder_propagation
- propagate a known order of input/output pins within module pin groups to other connected modules
- decorators
BooleanFunctionDecorator
- substitute power and ground nets/pins by constant values in Boolean functions via
substitute_power_ground_nets
andsubstitute_power_ground_pins
- get a concatenated Boolean function corresponding to a vector of nets or Boolean functions via get_boolean_function_from`
- substitute power and ground nets/pins by constant values in Boolean functions via
BooleanFunctionNetDecorator
- get a unique Boolean function variable for a net via
get_boolean_variable
andget_boolean_variable_name
- get the net corresponding to a unique Boolean function variable via
get_net_from
- get the net ID corresponding to a unique Boolean function variable via
get_net_id_from
- get a unique Boolean function variable for a net via
SubgraphNetlistDecorator
- copy a subgraph of the netlist via
copy_subgraph_netlist
- get the Boolean function of a subgraph via
get_subgraph_function
- get the inputs to the Boolean function of a subgraph without computing the Boolean function via
get_subgraph_function_inputs
- copy a subgraph of the netlist via
- miscellaneous
- added functions
get_pin_names
,get_input_pins
,get_input_pin_names
,get_output_pins
, andget_output_pin_names
to classModule
- added function
BooleanFunction::get_truth_table_as_string
that returns the truth table of a Boolean function as a formatted string - added missing GND, VCC, and RAM gate types to the
ICE40ULTRA
gate library - added Python bindings for the HAL project manager
- added new GUI dialog for creating an empty project (without providing a netlist)
- changed all example netlists to be HAL projects
- API cleanup for plugin
solve_fsm
- added functions
- bugfixes
- fixed Verilog and VHDL parser ignoring pin order of modules
- fixed order of module pins in Verilog writer
- fixed some errors in the Python documentation
- fixed pin types of
power
andground
gate types in various gate libraries - fixed spamming the log with messages related to module pins
- fixed segfault that sometimes occurred when deleting a module
- fixed saving absolute paths for Python files and not copying them to the new project folder when using
Save as...
- fixed some project manager bugs related to inaccessible files
- fixed missing Python binding for
GateType::get_pin_groups
- fixed incorrect undo action for “fold parent module”
- fixed some internal data structure of the Verilog and VHDL parsers not being cleared after each instantiation attempt
- fixed wrong gate type properties for MUX gates in various gate libraries
- fixed net and instance aliasing in VHDL and Verilog parser
- fixed netlist parser bug related to unconnected module pins that are being directly assigned to another wire/signal in the module/entity body
- fixed
get_pins
returning pins in wrong order if no filter is specified
Install && Tutorial
Copyright (c) 2019 Ruhr-Universität Bochum, Lehrstuhl für Eingebettete Sicherheit. All Rights Reserved.
Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann (“ORIGINAL AUTHORS”). All rights reserved.