Introduction to Memory Addressing Mode

In the memory addressing principle article, i introduced the basic knowledge of memory addressing , the memory addressing mode to look at IA-32-bit system addressing mode.

3. IA-32-bit system addressing mode

So far has introduced the basic address of the conversion of the linear address to the physical address and the data structure of the application. The above diagram is only given a linear address to the physical address conversion of a general process; for different systems, in fact, there are many differences in the process of address conversion, followed by different systems, combined with examples to introduce the specific way of address translation.

3.1 IA-32-bit system addressing mode diagram

32 system is currently the largest domestic use of the system. For the 32-bit system 4K page, the following is a screenshot from the Intel 64 and IA-32 Architectures Software Develper’s Manual:

And the previous diagram is very similar to the previous diagram is to use 32-bit system to explain the examples.

The linear address address is assigned as follows: 1. The 10-bit (bit 22-31) page directory table index is used to index the corresponding entry in the page table of contents. 2. The 10-bit (bit 12-21) page table index is used to index the corresponding entry in the page table. 3. 12-bit (bit 0-11) of the page offset, which is the same as before.

Analysis of the address conversion process: from the figure we can see the linear address is divided into three copies.

1. First by the CR3 register to get the page directory table pointer.
2. The upper 10 bits of the linear address are the index of the page directory to find the corresponding entry PDE.
3. The page table is positioned according to the PDE (taking the upper 20 bits of the PDE, the lower 12 bits 0).
4. Take the middle 10 bits of the linear address and fetch the entry PTE of the page table as the index of the page table.
5. Locate the memory page according to PTE (take the upper 20 bits of PDE, lower 12 bits).
6. The last 12 bits of the linear address are added to the memory page base address to add the physical address.

3.2 IA-32-bit system linear address and physical address conversion examples

According to the previous section, the following is an example of analyzing a linear address to a physical address translation. The idea is to first look at the value at that address by a linear address, then convert the linear linear address to a physical address, Is the same as the previous value.

To an addr_v2p program, for example, casually find a linear address 0x3015d5, as shown below:

Red arrow is the address corresponding to the value of 0xd2e85156, then look at the corresponding address of the physical address is not the value of this.

1. Find the page table according to CR3:

From the figure to see the page directory table only one page directory entry PDE, this is because we this procedure is very small, just to verify the address conversion process, so occupy a page directory entry can be.

2. Set the upper 10 bits of the linear address as the index of the page directory to find the corresponding PDE.

In the figure, the first 10 bits are 0, which means that the linear address corresponds to the first page directory entry (above also, there is only one page directory entry).

3. Position the page table according to the PDE (take the upper 20 bits of the PDE and the lower 12 bits).

PDE = page directory table base address + page table index = 0x344c000 + 0x0 = 0x344c000;

The corresponding page table base address is 0x1ca6b000 (page table occupies 20 bits high).

4. Take the middle 10 bits of the linear address and remove the entry PTE of the page table as the index of the page table.

The middle of the 10 is just 0x301 as an index, that is, 302 items.

5. Locate the memory page according to PTE (take the 20 high and low 12 bits of PDE).

At this point the positioning page table entry = page table base address + page table index = 0x1ca6b000 + 0x301 * 4 (each account occupies 4 bytes) = 0x1ca6bc04.

The entry corresponds to 0x19ac7025, and the PTE entry 0x19ac7025 corresponds to the memory page base address 0x19ac7000.

6. Take the last 12 of the linear address at the memory page base address to add the physical address.

The last 12-bit page offset is 0x5d5, the corresponding page is 0x19ac7000; the corresponding physical address is 0x19ac75d5. The physical address of the value as follows:

From the value of the physical address, we can see that the value in the linear address is the same as the value of the corresponding physical address. Note that conversion from a linear address to a physical address is completely correct.

4.IA-32 PAE mode addressing mode

The current user to use the most or win7 operating system, 32-bit win7 operating system can use up to the physical memory 4G, in order to be able to make more than 4G of the physical memory need to open PAE mode (in other articles have been described in detail PAE concept and Use, here is no longer cumbersome).

4.1 IA-32 PAE addressing mode diagram

After opening the PAE mode, the physical address can be 52 bits, 40 bits, and 36 bits, depending on the Intel 64 and IA-32 Architectures Software Develper’s Manual. The physical address is addressed to 36 bits in the PAE mode in win7 For example, the maximum addressing space 64G; the conversion of the linear address to the physical address is changed from the secondary mapping to the three-level mapping, and more than one page table pointer; according to “Intel 64 and IA-32 Architectures Software Develper’s Manual”

The above figure is a 32-bit system PAE mode, the linear address to the physical address of the conversion map. It can be seen from the figure that the linear address is divided into four parts. In IA-32 non-PAE mode, CR3 is the page directory pointer, pointing to the page directory table. In PAE mode, there is a more level of page directory pointer table, CR3 is the page directory pointer pointer, pointing to the page directory pointer table (PDPT).

The page directory pointer table contains four 8-byte entries (PDPTE).

The linear address address is assigned as follows:

1. 2-bit (bit 30 and bit 31) of the page directory pointer table index, used to index the address in the page directory pointer table corresponding entries.
2. 9-bit (bit 21-29) of the page directory table index, used to index the address in the table of contents in the table table corresponding entries.
3. 9-bit (bit 12-20) page table index, used to index the address in the page table in the corresponding entry.
4. 12 bits (bits 0-11) of the page offset, which is the same as before.

Analyze the address translation process:

1. First by the CR3 register to get the page directory pointer pointer.
2. Take the upper 30-31 bits of the linear address as the index of the page directory pointer table to find the corresponding entry PDPTE.
3. Position the page table according to PDPTE (take 12-35 bits of PDPTE).
4. Take the 21-29 bits of the linear address to find the corresponding table entry PDE for the index of the page table of contents.
5. The page table is positioned according to the PDE (taking the upper 20 bits of the PDE, the lower 12 bits 0).
6. Take the middle of the linear address 12-20 bits, as the page table index to remove the table table entry PTE.
7. Locate the memory page according to PTE (take the upper 20 bits of PDE, lower 12 bits).
8. The last 12 bits of the linear address are added to the memory page base address to add the physical address.

4.2 IA-32 PAE Mode Linear Address and Physical Address Translation Example

According to the diagram in the previous section, the following analysis of a PAE mode, PAE mode, the physical address from the original 4G expanded to 64G; linear address to the physical address conversion example, the idea is: first through a linear address to see the Address the value, and then the linear linear address is converted to a physical address, and then see if the value of the same with the previous value.

To an addr_v2p program, for example, PAE mode linear address is still 32, such as the linear address 0xde13a0, as shown below:

Red arrow is the address corresponding to the value of 0x81ec8b55, then look at the linear address of the corresponding physical address is not the value.

1. According to CR3 find the page directory pointer table:

As you can see from the figure, there are four entries in each page directory pointer table. Each entry is 8 bytes (64 bits). Therefore, you can know that the first two lines above are the page directory pointer table of the process.

2. Find the corresponding table entry PDPTE by taking the upper 30-31 bits of the linear address as the index of the page directory pointer table.

The red box in the figure shows that the first two bits are 0, which means that the linear address corresponds to the first page directory pointer entry.

3. Positioning the table of contents according to PDPTE (taking 12-35 bits of PDPTE).

PDPTE = page directory pointer table base + page directory table index = 0x3f2f23c0 + 0x0 = 0x3f2f23c0, the corresponding page directory pointer entry is 0x00000000’0370d801, the corresponding page directory base address is 0x370d000 (page directory which accounted for 12-35 bits ).

4. Take the 21-29 bits of the linear address to find the corresponding entry PDE for the index of the page table of contents.

The middle of the 9 is just 6 as an index. For item 7 of the page table.

5. Position the page table according to the PDE (take the upper 20 bits of the PDE and the lower 12 bits).

At this point the positioning page directory entry = page directory table base address + page table index = 0x00000000’0370d000 + 6 * 8 (each account occupies 4 bytes) = 0x00000000’0370d030.

The entry bound to 0x0000000016f33867. The page directory entry address is 0x16f33000 (page table is 12-35 bits).

6. Take the 12-20 bits in the middle of the linear address and remove the entry PTE of the page table as the index of the page table.

The middle of the 9 is just 0x1e1 as an index, then locate the page table entry = page table base + page table index = 0x0000000016f33000 + 0x1e1 * 8 (4 bytes per entry) = 0x16f33f08.

7. Position the memory page according to PTE (bit 12-35).

The entry PTE corresponds to 0x346f8025. The base address of the page is 0x346f8000 (page frame is 12-35 bits)

8. Take the last 12 bits of the linear address at the memory page base address to add the physical address.

The last 12 bits of the page offset is 0x3a0, the corresponding page is 0x346f8000; the corresponding physical address is 0x346f83a0. The physical address of the value as follows:

From the value of the physical address, we can see that the value in the linear address is the same as the value of the corresponding physical address. Note that conversion from a linear address to a physical address is completely correct.

5. IA-32E addressing mode

5.1 IA-32E addressing mode diagram

In the X86-64 architecture described in “Intel 64 and IA-32 Architectures Software Develper \ s Manual”, it is important to note that the x86_64 linear address is not 64 bits, the physical address is not 64 bits, and the Intel current CPU is the highest The address is 52 bits, but the actual support for the physical memory bus is 40 bits. Its physical address can also be 52, 40, 36 or so. ** why **** 40 * \ * bit physical memory bus bandwidth can be addressed **** 52 * \ * bit physical memory, this is because the physical memory bus bandwidth does not include the page address offset Address, page address offset occupies **** 12 * \ * bit, so **** 40 +12 * \ * just **** 52 **** bit physical address. ** to address the common address of the win7 64-bit address for 36, for example, the maximum addressing space 64G; linear address to the physical address of the conversion by the four mapping, than the three-level mapping by a page mapping four (PML4T (page map level4 tables)); according to “Intel 64 and IA-32 Architectures Software Develpers Manual”

The figure above is a conversion diagram of a linear address to a physical address in a 64-bit system. It can be seen from the figure that the linear address is divided into five parts. In PAE mode, CR3 is the page directory pointer pointer, pointing to the page directory pointer table (PDPT). In 64-bit mode, the CR3 register occupies 64 bits as the PML4T (Page-Map Level 4_) mapping table pointer. But in the win7 64-bit system, only the use of 24 of them to address the PML4T.

PML4T is a 64-bit system to increase the structure, through the PML4T to find the corresponding PDPTE.

The linear address address is assigned as follows:

1. 9 bits (bits 39-47) of the PML4T index, used to index the address in the PML4T in the corresponding entry.
2. 9-bit (bit 30-38) page directory pointer table index, used to index the address in the page directory pointer table corresponding entries.
3. 9-bit (bit 21-29) of the page directory table index, used to index the address in the table of contents in the table table corresponding entries.
4. 9-bit (bit 12-20) page table index, used to index the address in the page table in the corresponding entry.
5. 12-bit (bit 0-11) page offset.

Analyze the address translation process:

1. The PML4T pointer is calculated first by the CR3 register (bits 12-35).
2. Take the 39-47 bits of the linear address for the PML4T index to find the corresponding entry PML4TE.
3. Positioning the page directory pointer table according to PML4T (take 12-35 bits of PDPTE).
4. Take the 30-38 bits of the linear address to find the corresponding entry PDPTE for the index of the page directory pointer table.
5. Position the page table according to PDPTE (take 12-35 bits of PDPTE).
6. Take the 21-29 bits of the linear address to find the corresponding table entry PDE for the index of the page table of contents.
7. The page table is positioned according to the PDE (taking the upper 20 bits of the PDE, the lower 12 bits 0).
8. Take the middle of the linear address 12-20 bits, as the page table index to remove the table table entry PTE.
9. Locate the memory page according to PTE (take the upper 20 bits of PDE, lower 12 bits).
10. The last 12 bits of the linear address are added to the memory page base address to add the physical address.

5.2 IA-32E system linear address and physical address translation examples

According to the previous section, the following analysis of a 64-bit mode in the case of a linear address to the physical address conversion, verify the idea is: first through a linear address to view the address out of the value, and then linear linear address into a physical address, And then see if the value is the same as the previous value.

To a FuncParaX64 program, for example, 64-bit mode linear address representation of 64-bit, such as the linear address rsp = 0000000000affe88, as shown below:

In the rsp address 0x00000000 \ ’00affe88 save the first four bytes of the value of 0xe9331262, then look at the linear address of the corresponding physical address is not the value.

1. The PML4T mapping table pointer is calculated first by the CR3 register (bits 12-35)

CR3 register is 0x5d8ff000, its 12-35 bit or 0x5d8ff000, said PML4T address, as shown below

The first entry of the PML4T table is 0x030000005a3b8867.

2.Take the 39-47 bits of the linear address for the PML4T index to find the corresponding entry PML4TE.

It can be seen that the value of 39-47 bits of 64-bit linear address is 0, that is, the first entry in PML4T points to PDPT table. From the above figure, we can see that the offset of the entry should be 0x5d8ff000 + 0 * 8 (8 bytes per table of PML4T) = 0x5d8ff000, the contents of the entry are 0x031000005d1d5867:

3. Positioning the page directory pointer table according to PML4TE (taking bits 12-35 of PML4TE).

The PML4TE table corresponds to the page directory pointer table base address (take PML4TE 12-35 bits) as follows:

4. Find the corresponding table entry PDPTE by taking the 30-38 bits of the linear address as the index of the page directory pointer table.

The red box in the figure shows that its 30-38 bits are 0, which means that the linear address corresponds to the first page directory pointer entry.

5. Locate the page table according to PDPTE (take PDPTE 12-35 bits).

PDPTE = page directory pointer table base address + page directory table index = 0x5d1d5000 + 0x0 * 8 = 0x4d1d5000, the corresponding page directory pointer entry is 0x03200000 \ ‘5e5d6867.

Then the page directory table base address is 0x5e5d6000 (page directory table occupies 12-35 bits in the page directory pointer entry).

6. Take the 21-29 bits of the linear address to find the corresponding entry PDE for the index of the page table of contents.

The middle of the 9 is just 5 as an index.

7. Position the page table according to the page directory entry in PDE (take 12-35 bits of PDPTE).

In this case, the page directory entry is the value of the page directory table. Table Contents Table Base Table + Table Table Index = 0x5e5d6000 + 5 * 8 (4 bytes per entry) = 0x5e5d6028, the page table entry value is 0x01700000 \ ’24c5d867.

Then the page table base address is 0x24c5d000 (page table occupies 12-35 bits in the page directory entry).

8. Take the 12-20 bits in the middle of the linear address and remove the entry PTE of the page table as the index of the page table.

The middle of this 9 is just 0xff as an index, then locate the page table entry address = page table base address + page table index = 0x24c5d000 + 0xff * 8 (each 8 bytes) = 0x24c5d7f8.

9. Locate the memory page according to the memory page base address (12-35 bits) in the PTE.

The page table entry address = 0x24c5d7f8, the page directory entry value is 0x827000000 \ ’35f69847.

Then the memory page base is 0x35f69000 (memory page occupies 12-35 bits in the page table entry).

10. Take the last 12 of the linear address at the memory page base address to add the physical address.

The last 12-bit page offset is 0xe80, the corresponding page is 0x35f69000; the corresponding physical address is 0x35f69e88. The physical address of the value as follows:

From the value of the physical address, we can see that the value in the linear address is the same as the value of the corresponding physical address. Note that conversion from a linear address to a physical address is completely correct.

6. Summary

Finally summarize the IA-32, IA-32 PAE, IA-32E three modes used in the structure:

1. IA-32: linear address, CR3 register, page table of contents (PDT), page directory entry (PDE), page table (PT), page table entry (PTE).
2. (PDP), page directory entry (PDP), page directory (PDP), page directory (PDP), page directory entry (PTE).
3. (PDPT), page directory pointer table (PDPT), table name table (PDPT), page name table (PDPT), page name table (PDPT) , Page directory entry (PDE), page table (PT), page table entry (PTE).