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The UCIe Industry Consortium—comprising Intel, AMD, Microsoft, Meta, Google, Qualcomm, Samsung, TSMC, ASE, and other leading technology firms—has unveiled the new UCIe 3.0 open chiplet interconnect standard, elevating data transfer rates from the previous 32 GT/s to 48 GT/s and 64 GT/s. This leap is designed to meet the stringent high-bandwidth, low-latency requirements of next-generation chiplet architectures for AI, high-performance computing (HPC), and other advanced workloads.
Compared with the UCIe 2.0 specification announced in August last year, UCIe 3.0 not only delivers substantial bandwidth improvements while maintaining full backward compatibility, but also introduces a host of architectural and functional enhancements.
Notably, it incorporates an advanced runtime recalibration mechanism that enables power-efficient link adjustments without the need for reinitialization, thereby improving overall system performance. The standard also extends the marginal channel length to 100 mm, facilitating more diverse system-in-package (SiP) topology designs.
On the transmission side, UCIe 3.0 strengthens data interoperability between chiplets and components such as SoCs and DSPs through continuous transport protocol mapping and support for raw mode. It also enables early firmware downloads via standardized Multi-Tile Programming (MTP) processes, streamlining the development phase.
For time-sensitive computing applications, UCIe 3.0 introduces a prioritized sideband packet mechanism to ensure the real-time, low-latency delivery of critical system events. Additionally, its fast-throttle and emergency-shutdown designs support open-drain (OD) I/O signaling for immediate system-level alerts, further bolstering stability and security.
Since its establishment in 2022, the UCIe Industry Consortium has emphasized building an open, standardized, and flexible chiplet interconnect framework based on widely adopted technologies like PCIe and CXL, enabling the semiconductor industry to transition from traditional monolithic chips to modular, chiplet-based architectures.
The release of the UCIe 3.0 specification is expected to accelerate innovation and deployment in high-performance computing, artificial intelligence, and advanced packaging technologies across the semiconductor design landscape.
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