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In a bid to demonstrate that it can truly rival TSMC in the foundry arena, Intel recently released a conceptual technology video through Intel Foundry, unveiling its next-generation hybrid packaging vision. The concept combines the not-yet-mass-produced 14A process with the forthcoming 18A node, promising the ability to integrate up to 16 processors and 24 stacks of high-bandwidth memory (HBM) within a single package—an extraordinary display of scalability and computational density.
In Intel’s vision, this “super chip” is not built on a single manufacturing node, but instead fully exploits the advantages of heterogeneous chiplet integration:
- Compute Tiles: Fabricated using the next-generation 14A-E process, these tiles incorporate RibbonFET 2 (second-generation gate-all-around transistors) alongside PowerDirect backside power delivery, and are responsible for the primary performance output.
- Base Die: Serving as the foundation, this layer is produced on the 18A-PT process, which introduces PowerVia backside power delivery for the first time.
To bind these disparate dies together while ensuring ultra-high-speed signal transfer, Intel employs its proprietary Foveros Direct 3D stacking technology in tandem with EMIB-T (Embedded Multi-die Interconnect Bridge). This approach allows chip designs to resemble high-rise architecture: compute units stacked vertically, while memory and I/O are bridged horizontally. The video highlights a twelvefold reticle scalability, implying the capability to manufacture chips several times larger than today’s single-reticle limits.
At its most extreme configuration, the package can house 16 high-performance compute dies, surrounded by 24 HBM stacks supporting the latest memory interconnect standards. Such specifications are clearly not aimed at consumer-grade Core processors, but squarely at the immense demands of data centers and AI model training. Intel’s decision to release this video toward the end of 2025 carries unmistakable strategic intent.
As NVIDIA, AMD, and even cloud giants such as Google, Microsoft, and AWS increasingly invest in in-house AI silicon, demand for advanced packaging technologies—like TSMC’s CoWoS—has begun to outstrip demand for advanced process nodes alone. Intel’s message to prospective customers is unambiguous: it can not only manufacture cutting-edge 18A or 14A chips, but also deliver a complete, end-to-end “system foundry” service encompassing packaging, stacking, and testing.
In today’s AI chip arms race, memory bandwidth and interconnect speed are often the true performance bottlenecks. Intel’s demonstration of accommodating 24 HBM stacks is a direct appeal to customers constrained by CoWoS capacity or technical limitations.
Yet, as impressive as such technological showcases may be, the market’s attention ultimately rests on execution. Whether Intel can successfully mass-produce its first 18A consumer product—Panther Lake—and deliver the promised performance will be the decisive first step in determining whether Intel Foundry can truly earn customer confidence.
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